![]() ![]() ![]() On the HIP6602B, the upper gate 2 (phase 2) was s/c to the I found on the HIP6601B, the upper gate drive was s/c to To see if phase and the upper gate on each device for each phase were s/c. Side appear to be common to the gate and the sources are allĪs the FETs appear to be in good condition, I checked the drivers I did a quick check (in cct) of the FETs for shorts and the upper Reduces switching losses in the high-side FET and ![]() So this is an asymmetric topology for obvious reasons such as ġ. The Lower Gate on the HIPs drives six (from my inspection) The Upper Gate on the HIPs drives three for the three phases I have 9 On Semiconductor NTD60N02R Power MOSFETs. The former package can drive 1 phase and the latter This can drive up to 4 phases - this mobo has 3 The VRM has an Intersil ISL6556B controller ![]()
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